Not sure why the Chip-Scale Atomic Clock (CSAC) is making news again; this seems to be a rehash of news from January, but it’s an opportunity to make a few comments.

One of the sessions I attended at the recent timing conference discussed some of the pros and cons of the new competitors to the traditional quartz oscillator, one being the CSAC and the other being microelectromechanical systems (MEMS). CSACs have a niche because of the desire to optimize on several variables such as cost, power, stability, and startup requirements. A good quartz oscillator, for example, needs a relatively long warmup time, and the ones with good stability are expensive and tend to drift a bit. So there’s room to beat it on some variables, depending on what the user needs vs. what s/he doesn’t care about, e.g. power and size are variables that matter for a portable system but not for a server rack.

One of the observation is that CSACs could soon find their way into computers tied into ultra-high speed networks, because the clock performance becomes a limiting factor in data transfer — you can send data at a higher frequency and you spend less time re-synchronizing the clocks.

Another observation was a reminder that DARPA is currently funding another program to drive the size and power down even further.